1. Field of Invention
This invention relates to digital circuits, specifically to improved performance, reduced power dissipation and improved circuit robustness for digital logic circuits.
2. Prior Art
Improved performance, reduced power dissipation, and circuit robustness are key objectives of semiconductor circuit design. Often these objectives are contradictory and require tradeoffs of one objective relative to another. Complementary digital logic such as CMOS is very robust but performance and power are negatively affected by large parasitic capacitances and crow-bar currents that flow during logic transitions. Dynamic logic has high performance characteristics because it utilizes discharge of a precharged node to change the logic state of the output. This allows a fast transition on the output because parasitic capacitances are smaller and there is no need to turn off competing pull-up or pull-down transistors as the input transitions from LOW to HIGH or from HIGH to LOW, respectively. This fight between pull-up and pull-down during the input transitions tends to slow down output transitions for standard gates implemented with complementary logic switches or transistors. The fight between the pull-up and pull-down transistors during the input transition also increases power dissipation due to the crow-bar current that flows directly through the pull-up and pull-down transistors both of which are partially ON during the transition period. This is especially true if input transitions are slow.
Dynamic Logic has disadvantages that compromise robustness and limit applicability in the case of modern high-leakage technologies. High leakage limits the maximum time interval between precharge turn-off and logic state evaluation. In the limit of high leakage this interval can become vanishingly small. Also, dynamic logic suffers from the constraints of charge sharing. This can further reduce the margin for maintaining the precharge level under worst-case conditions.